1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device comprising a capacitor as a capacitive element in an interconnect structure, and more particularly relates to a semiconductor integrated circuit device, which is preferably applied to a static random access memory (SRAM) comprising a capacitor.
2. Related Art
In modern semiconductor integrated circuit devices, efforts for reducing the supply voltage to about 1.0 to 2.1 volts are conducted, and in order to meet the needs, a miniaturization of the device size and the interconnect line width for various devices is developed. For example, in the case of SRAM, a scale reduction of the memory cell and a scale reduction of the interconnect line width coupled thereto is developed. While the scale reduction of the interconnect line width and the memory cell provides a decrease of resistivity of the interconnect that provide a coupling between various elements, and thus is effective in view of achieving high-speed operation, an interconnect capacitance is adversely increased, and thus a disadvantage on element characteristics may be generated. For example, in a SRAM cell consisting of six MOS transistors Q1 to Q6 shown in FIG. 10, accumulation of data is conducted by utilizing capacitance which is parasitic on interconnects N1 and N2 (hereinafter, the type of interconnects such as the interconnects N1 and N2 are referred to as “node interconnects”, and the node interconnect means an interconnect, being coupled to a node, to which respective drains of the load transistor Q1 and the driving transistor Q3 are coupled, and an interconnect, being coupled to a node, to which respective drains of the load transistor Q2 and the driving transistor Q4 are coupled), which cross-couples a gate and a drain of a pair of driving transistors Q3 and Q4 that reciprocally turn on and off. (hereinafter referred to as “node capacitance”) However, a size of a diffusion layer for forming a node capacitance is decreased as the memory cell size and the line width size (gate area) are reduced, and, in turn, the node capacitance is decreased, and thus a problem of a soft-error is occurred. The soft-error is a phenomenon, in which, when a ray and neutron beam are irradiated on the memory cell, data electric charge accumulated in the node capacitance escapes away toward the semiconductor substrate side and thereby dissipating the data.
To address the soft-error problem, Japanese Patent Laid-Open No. H10-163,440 (1998) discloses a technology of forming a multi-layered structure by laminating respective node interconnects (node interconnects N1 and N2 in the example shown in FIG. 10) of a pair of driving transistors that compose a memory cell, partially containing an insulating layer therebetween, and a capacitor is composed of the multi-layered structure, and a capacitance, which is parasitic on the node interconnect by this capacitor, or in other words a node capacitance, is increased. Since the accumulated data electric charge is increased by the increase of the node capacitance, a SRAM having higher soft-error resistance can be obtained without increasing the size of the memory.
In addition, in order to increase the node capacitance of the memory cell, Japanese Patent Laid-Open No. 2002-324,855 proposes a technology of: forming a node interconnect by forming a trench in an insulating film formed on the semiconductor substrate and filling the trench with an electrically conducting film; and forming a first electrode having a plug shape partially in this node interconnect, and after exposing the upper end portion of the first electrode for over a predetermined height thereof, consecutively forming the capacitance insulating film and the second electrode to cover the exposed portion. In the disclosure of Japanese Patent Laid-Open No. 2002-324,855, since the capacitor is composed by utilizing the upper surface and the side surfaces of the first electrode, the area thereof facing to the second electrode can be increased, thereby providing an advantageous effect in view of increasing the node capacitance. In addition, since the capacitance insulating film and the second electrode are flat on the first electrode, the capacitance insulating film composing the capacitor can be formed to a uniform film thickness, thereby improving the reliability of the capacitor.
However, since the respective node interconnects of pair of the driving transistors are required to be formed as layered structures in the aforementioned technology disclosed in Japanese Patent Laid-Open No. H10-163,440, the node interconnects must be formed to be dual layers. Therefore, as compared with the former SRAM, in which both node interconnects are formed in one layer, the pattern of the node interconnect should be changed, and an additional process step for manufacturing a contact for electrically coupling the node interconnect formed in the upper layer side to the transistor is required, thereby adversely increasing the process steps. Further, since the capacitor is composed only in a crossing region of both node interconnects, it is difficult to take larger areas of facing electrodes, and thus, there is a limitation in increasing the node capacitance.
In addition, since the technology disclosed in Japanese Patent Laid-Open No. 2002-324,855 involves forming both node electrodes of pair of driving transistors in the same layer, the node capacitance can be increased without changing the pattern of the node interconnect in the SRAM. However, even though the capacitance insulating film and the second electrode are flatly formed on the upper surface of the first electrode in the formed capacitor, unwanted step portions may be generated in the capacitance insulating film and the second electrode along the side surfaces and their circumferences of the first electrode, since the upper end portion of the first electrode is exposed over a predetermined height in order to increase the node capacitance. Therefore, when the sizes of the memory cell and the line widths of the node interconnect are reduced, and concurrently the film thicknesses of the capacitance insulating film and the node interconnect are reduced, defects in the steps are easily occurred in the capacitance insulating film and the second electrode in the above-described step portion, thereby causing a decrease of the manufacturing yield for the memory cell and a decrease of the reliability thereof.